With semiconductor devices, in particular with memory devices such as DRAMS (DRAM=Dynamic Random Access Memory or dynamic read-write memory, respectively)—based e.g. on CMOS technology—, so-called clock signals are used for the chronological coordination of the processing or relaying, respectively, of the data.
In the case of conventional semiconductor devices, a single clock signal—that is present at a single line—is, in general, used (i.e. a so-called “single-ended” clock signal).
The data may then be relayed e.g. at the respective rising clock edge of the single clock signal (or, alternatively, e.g. at the respective falling clock edge of the single clock signal).
Furthermore, so called DDR devices, in particular DDR-DRAMs (DDR-DRAM=Double Data Rate—DRAM or DRAM with double data rate, respectively), are already known in prior art.
In the case of DDR devices—instead of one single clock signal present at a single line (“single-ended” clock signal)—two differential, oppositely-inverse clock signals present on two separate lines are used.
Whenever, e.g., the first clock signal of the two clock signals changes from a state “logic high” (e.g. a high voltage level) to a state “logic low” (e.g. a low voltage level), the second clock signal changes—substantially simultaneously—its state from “logic low” to “logic high” (e.g. from a low to a high voltage level).
Vice versa, whenever the first clock signal changes from a state “logic low” (e.g. a low voltage level) to a state “logic high” (e.g. a high voltage level), the second clock signal (again substantially simultaneously) changes its state from “logic high” to “logic low” (e.g. from a high voltage level to a low voltage level).
In DDR devices, the data are, in general, relayed both at the rising edge of the first clock signal and at the rising edge of the second clock signal (or both at the falling edge of the first clock signal and at the falling edge of the second clock signal, respectively).
Thus, relaying of the data in a DDR device is performed more frequently or more quickly, respectively (in particular twice as frequent or twice as quick, respectively) than with corresponding, conventional devices with a single or “single-ended” clock signal, i.e., the data rate is higher, in particular twice as high, as with corresponding, conventional devices.
The clock signal used—internally—in the device for the chronological coordination of the processing or relaying, respectively, of the data (“DQS” signal or “data strobe” signal, respectively) (or—when differential, oppositely-inverse clock signals are used—the internal clock signal DQS and the clock signal BDQS that is oppositely-inverse to the clock signal DQS) must be synchronous to a clock signal (“CLK” signal or “clock” signal, respectively) input externally into the device (or synchronous to the differential clock signals CLK, BCLK input externally into the device, respectively).
The external clock signal(s) CLK, BCLK is/are generated by an appropriate clock signal generator connected with the device.
For synchronizing the internally generated clock signal DQS or the internally generated clock signals DQS, BDQS, respectively, with the external clock signal(s) CLK, BCLK, a clock signal synchronizer, e.g. a DLL circuit (DLL=Delay-Locked-Loop) is used. Such a circuit is, for instance, known from EP 964 517.
A clock signal synchronizer may, for instance, comprise a first delay means into which the external clock signal(s) CLK, BCLK is/are input, and which charges the input clock signal(s) CLK, BCLK—as a function of a control signal output by a phase comparator—with a variable delay time tvar that is adjustable by the control signal.
The signal(s) output by the first delay means may be used—internally—in the device for the chronological coordination of the processing or relaying, respectively, of the data (i.e. as—internal—clock signal(s) DQS or BDQS, respectively).
The signal DQS output by the first delay means is supplied to a second delay means that charges the input signal DQS with a—fixed—delay time tconst corresponding approximately to the sum of the signal delays caused by the receiver(s) (“receiver delay”), the respective data path (“data path delay”), and the off-chip driver(s) (“OCD delay”).
The signal output by the second delay means (FB signal or “feedback signal”, respectively) is supplied to the above-mentioned phase comparator; there, the phasing of the FB signal is compared to that of the CLK signal that has also been input into the phase comparator. Depending on whether the phase of the FB signal hurries ahead or runs after that of the CLK signal, the phase comparator outputs—as a control signal for the above-mentioned first delay means—an incrementing signal (INC signal) or a decrementing signal (DEC signal), which result in that the delay tvar of the CLK signal effected by the first delay means is—in the case of an INC signal—incremented, or—in the case of a DEC signal—decremented, so that the CLK signal and the FB signal are finally synchronized, i.e. the clock signal synchronizer is “locked.”
For instance, in a first phase (when the positive edge of the FB signal (still) runs after the positive edge of the CLK signal), the phase comparator may initially generate an INC signal resulting in that the delay tvar caused by the first signal delay means is incremented—relatively strongly—, or the phase rate of the FB signal is incremented—relatively strongly—vis-à-vis the phase rate of the CLK signal, respectively (“coarse adjustment”).
When the positive edge of the FB signal “overtakes” the positive edge of the CLK signal, the phase comparator may generate a DEC signal resulting in that the delay tvar caused by the first delay means is (again) decremented, or the phase rate of the FB signal is decremented vis-à-vis the phase rate of the CLK signal (namely—for “fine adjustment”—only relatively slightly).
By the initially strong and then relatively weak changes of the delays tvar or phase shifts, respectively, caused by the first signal delay means, a relatively quick synchronization of the CLK and FB signals can—as a rule—be achieved, i.e. the clock signal synchronizer can be “locked” relatively quickly.
However—due to the signal delays occurring in the DLL circuit—the above-described decrementation of the FB signal phase rate caused by the DEC signal vis-à-vis the CLK signal phase rate is effected only some clocks (e.g. four clocks) after the positive edge of the FB signal has “overtaken” the positive edge of the CLK signal.
This may result in that the FB signal meanwhile hurries ahead the CLK signal so far (in particular that e.g. the positive edge of the FB signal has “overtaken” the negative edge of the CLK signal) that the phase comparator again outputs an INC signal, etc., etc., so that the CLK and the FB signals cannot be synchronized, i.e. the clock signal synchronizer cannot be “locked.”
For these and other reasons there is a need for the present invention.